1. Field of the Invention
The present invention relates to erasable programmable read only memory (EPROM) cell structures and, in particular, to a high density EPROM cell that substitutes tantalum oxide for conventional oxide-nitride-oxide ONO) composite as the control gate dielectric.
2. Discussion of the Prior Art
Traditionally, advances in the reduction of EPROM memory size have concentrated on pushing the limits of optical lithography and plasma etching in implementing the industry standard T-cell EPROM structures. These approaches, however, require the use of complicated technologies such as trench isolation schemes and local interconnects.
Self-aligned submicron cell structures have been recently introduced for multi-megabit high-density EPROMs. Examples of such cells are disclosed in the following publications: (1) A. T. Mitchell et al., "A New Self-Aligned Planar Array Cell for Ultra High Density EPROMs", IEDM Tech. Digest, pp. 548-551, 1987; (2) O. Belleza et al., "A New Self-Aligned Field Oxide for Multimegabit EPROMs", IEDM Tech. Digest, pp. 579-582, 1989; and (3) A. Bergemont et al., "A High Performance CMOS Process for Submicron 16 Meg EPROM", IEDM Tech. Digest, pp. 591-594, 1989.
Although these structures have proven the feasibility of 16 Meg EPROM cells in small geometries, the planarization of bit lines in the Mitchell et al. array and the reduction of bird's beak isolation in both the Belleza et al. and Bergemont et al. arrays still remain as major problems in further scaledown.
To address these problems, Bergemont has proposed a self-aligned, stack-etched cross-point EPROM cell for integration in a 16 Meg EPROM virtual ground array; A. Bergemont, "Process Flow Using Stacked Gate Process for Cross Point EPROM Cell with Internal Access Transistor", U.S. patent app. Ser. No. 687,176, filed Apr. 18, 1991 and commonly-assigned herewith.
However, beyond 16 Megabit densities, current oxide-nitride-oxide (ONO) control gate dielectric layers cannot be scaled down properly due to the low coupling ratio and high critical field introduced across the ONO. Therefore, it is necessary to develop a process flow for high density memories at the 64 Meg density level, and beyond, that uses a high dielectric material to replace the conventional ONO layers.
Recently, tantalum oxide has been extensively studied as a promising dielectric film for high-density DRAM applications because of its high dielectric constant (four or five times higher than that of silicon dioxide) and its dielectric strength. See, for example, S. Zaima et al., "Preparation and Properties of Ta.sub.2 O.sub.5 Films by LPCVD for ULSI Application", J. Electrochemical Soc., Vol. 137, No. 4, pp. 1297-1300, April 1990 and H. Shinriki et al., "UV-03 and Dry O.sub.2 : Two-Step Annealed Chemical Vapor-Deposited Ta.sub.2 O.sub.5 Films for Storage Dielectrics of 64 Mb DRAM's", IEEE Trans. on Electron Devices, Vol. 38, No. 8, pp. 455-462, March 1991.
FIGS. 1 and 2 show the layout and the equivalent circuit schematic, respectively, of a known cross-point EPROM cell structure.
An improved process flow for the cell structure shown in FIGS. 1 and 2 is the subject of the above-mentioned Bergemont U.S. pat. application Ser. No. 687,176. The Bergemont process integrates high density EPROMs without using aggressive technologies. In the basic Bergemont process flow, a stacked etch is used so that floating gate edges are self-aligned to the word lines. This eliminates any possible parasitic poly2 transistors and removes all of the process steps previously required to cope with problems inherent in the approach utilized in the FIG. 1/2 array, such as the requirements for a special boron array field implant and for isolation oxide.
However, because the Bergemont process uses ONO control gate dielectric layers, it cannot be easily integrated at 64 Meg density levels and beyond. As stated above, this is due to the fact that the conventional ONO layer does not provide enough dielectric strength with an adequate coupling ratio required for programming and reading high-density EPROM cells. Also, in the Bergemont process, the ONO dielectric layers are exposed to n+ bit line implantation, which may result in degradation of dielectric integrity.
The FIG. 1/2 process, which protects the ONO during n+ bit line implantation by using a polysilicon, and nitride cap, is too complicated and requires two definitions of poly1. Furthermore, the high resistance of the polysilicide word line results in low-speed operation.